1. Field of Invention
The present invention relates to a gate array. In particular, the present invention relates to a gate array that can minimize the number of pins of the gate array and the number of components outside the gate array.
2. Description of Related Art
FIG. 1(a) shows a top view of a conventional gate array. FIG. 1(b) shows an enlarged view of portion (B) of FIG. 1(a). The gate array comprises a core cell region 10, a power supply pattern 12, and an input/output cell region 16. The core cell region 10 has a plurality of logic gates. The power supply pattern 12 is provided beside the core cell region 10 for providing electrical power to the core cell region 10. The power supply pattern 12 has two parallel patterns, with the inside portion of the power supply pattern 12 being connected to the ground, and the outside portion of the power supply pattern 12 being connected to the power source VDD. The input/output cell region 16 is provided beside the power supply pattern 12. The input/output cell region 16 inputs and outputs data for the core cell region 10.
FIG. 2 shows an Axe2x80x94A cross sectional view of the gate array shown in FIG. 1(b). The core cell region 10, the power supply pattern 12, and the input/output cell region 16 are provided on a substrate 30. The core cell region 10 and the input/output cell region 16 are made by a transistor. The power supply pattern 12 is placed on the insulator 32, which is provided between the power supply pattern 12 and the substrate 30 to insulate the electric current between the two elements.
The region under the power supply pattern 12 is not used efficiently in conventional gate arrays. Here, the region under the power supply pattern 12 refers to the region between the substrate 30 and the insulator 32. To constitute a circuit such as phase-lock loop and an analog circuit within the gate array, a large capacitance and resistance are needed within the gate array. To enlarge the capacitance and resistance of the gate array, the area of the core cell region 10 must be made larger.
However, because the core cell region 10 is not designed to have high capacitance and resistance, but rather to have high operation speed, a large area of the core cell region 10 is used for providing necessary capacitance and resistance. Therefore, it is difficult to install circuits such as phase-lock loop within the gate array, and the number of gate array signal pins and the number of components outside the gate array is increased.
FIG. 3(a) shows a top view of another conventional gate array. FIG. 3(b) shows an enlarged view of the portion (B) in the FIG. 3(a). This gate array also comprises a core cell region 10, a power supply pattern 12, and an input/output cell region 16, but differs from the gate array of FIG. 1 and FIG. 3 in that a portion of the core cell region 10 is provided under the power supply pattern 12.
FIG. 4 shows an Axe2x80x94A cross sectional view of the gate array shown in FIG. 3(b). The core cell region 10a and 10b are provided on the substrate 30. The power supply pattern 12 is provided on the insulator 32, which is itself provided on the core cell region 10b to insulate the electric current between the power supply pattern 12 and the core cell region 10b. In other words, the core cell region 10b is provided between the substrate 30 and the power supply pattern 12.
The gate array of FIG. 3 comprises a larger core cell region 10 than does the gate array of FIG. 1. However, because the core cell region 10 is not designed to have a large capacitance or resistance, the core cell region 10 can not provide sufficient capacitance and resistance to a circuit such as a phase-lock loop that requires significant capacitance and resistance. It is therefore difficult to include a circuit such as phase-lock loop within the gate array, and the number of signal pins of gate array and the number of components outside the gate array will be increased.
Given these problems, it is an object of the present invention to provide a gate array which can minimize the number of pins of the gate array and can reduce the components outside of the gate array.
As stated, it is an object of the present invention to provide a gate array that is capable of solving the problems described above. The object of the present invention can be achieved by the combinations of features described in the independent claims of the present invention. The dependent claims of the present invention define further advantageous embodiments of the present invention
According to the first aspect of the present invention, a gate array comprises a core cell having a plurality of logic gates, a power supply pattern provided beside the core cell for providing electrical power to the core cell, and a border element provided beside the power supply pattern for providing capacitance or resistance to the core cell.
According to another aspect of the present invention, a gate array can be provided such that the border element has a capacity cell including a transistor for providing the capacitance to the core cell. The capacity cell can be provided under the power supply pattern.
According to a still other aspect of the present invention, a gate array can be provided which further comprises an input/output cell region provided beside the power supply pattern to input and output data for the core cell, and in which the capacity cell is provided between the power supply pattern and the input/output cell region.
A portion of the core cell can be provided under the power supply pattern. The border element may have a plurality of the capacity cells, and each of the capacity cells has substantially same capacitance with each other.
The border element may have a plurality of capacity cells, and each of the capacity cells may have a different capacitance. The capacitance of the capacity cell can be larger than capacitance of the core cell. Preferably, the width of the capacity cell is substantially equal to the width of the power supply pattern.
According to yet another aspect of the present invention, a gate array can be provided such that the border element has a resistor cell including a transistor that provides the resistance to the core cell. The resistor cell can be provided under the power supply pattern.
According to a still further aspect of the present invention, a gate array can be provided which further comprises an input/output cell region provided beside the power supply pattern to input and output data for the core cell, and wherein the resistor cell is provided between the power supply pattern and the input/output cell region. A portion of the core cell can be provided under the power supply pattern.
The border element may have a plurality of the resistor cells of substantially equal resistance. The border element may have a plurality of the resistor cells, and each of the resistor cells has different resistance with each other. The resistance of the resistor cell can be larger than resistance of the core cell.
According to yet another aspect of the present invention, a gate array can be provided such that the border element comprises a material that provides resistance to the core cell. The material can be provided under the power supply pattern.
The material can also be provided between the power supply pattern and the input/output cell region. A portion of the core cell can be provided under the power supply pattern. The border element may have a plurality of materials, and each may have substantially the same resistance, or the resistance of the materials may differ.
According to a still further aspect of the present invention, a gate array can be provided such that the border element has a capacity cell including a transistor that provides capacitance to the core cell, a resistor cell having-a transistor that provides resistance to the core cell, and a material having resistance to be provided to the core cell; The capacity cell, the resistor cell, and the resistor can be provided under the power supply pattern.